1. Field of the Invention
This invention relates to focal plane arrays, and particularly to focal plane readout unit cells.
2. Description of the Related Art
A focal plane array is made from an array of photodetectors that are coupled to respective "readout unit cells". The unit cells integrate the photocurrent produced by their respective photodetectors over a specific integration period, and the integrated currents are multiplexed and amplified to produce a single video output.
The unit cells are typically arranged into an array and integrated together on a common substrate. A capacitor within each unit cell performs the photocurrent integration, which is necessary to reduce the effect of photocurrent shot noise and improve signal-to-noise (S/N) ratio. Integrated capacitors, however, tend to have small capacitance values due to the small surface area typically allotted them. The small integrated capacitors have a very limited charge capacity, and thus may reach maximum charge before the integration period is over. To prevent the loss of signal information, the integration period must be kept short, which increases the effect of photocurrent shot noise and lowers S/N ratio.
The photocurrent output of a photodetector includes an inherent "background" component, with the signal information of interest riding on top of the background component. As such, some of the integrating capacitor's limited charge capacity is consumed by the unwanted background component. This background component is particularly large in the photocurrent produced by infrared-sensitive photodiodes, and the limited capacity of integrated unit cell capacitors is particularly troublesome for infrared focal plane arrays.
Several approaches to circumventing the limited charge capacity problem involve "skimming" some of the charge from the integrating capacitor. That is, some of the charge accumulating on the capacitor during an integration period is removed so that the capacitor can accommodate a higher maximum photocurrent, with the skimmed charge ideally comprising just the unwanted background component. One such approach involves connecting a MOSFET current source to the integrating capacitor. The MOSFET is operated continuously throughout each integration period to bleed off charge from the capacitor. There are several problems with this approach, however: with charge being withdrawn over the full integration period, typically about 8 ms, the MOSFET only need carry a very small current. To prevent the quantity of charge withdrawn from exceeding that due to the background component, the MOSFET must be operated in its weak inversion mode, where the drain current is exponentially related to the effective gate drive--i.e., the gate voltage minus the MOSFET's threshold voltage (V.sub.gs -V.sub.th). However, due to processing variations, there is some variability in the threshold voltages of the focal plane array's charge skimming MOSFETs. Because of the exponential relationship, the threshold variability can cause the amount of charge skimmed to vary widely from cell to cell, rendering the technique virtually unusable. Furthermore, the low MOSFET transconductance and the long charge skimming period serve to increase the amount of noise contributed by each MOSFET.
Another approach is described in U.S. Pat. 5,128,534 to Wyles, et al. Conventionally, one terminal of the integrating capacitor is connected to the photocurrent and the other terminal connected to ground. The Wyles circuit takes the terminal which is normally grounded and connects a ramping voltage to it instead. This voltage is ramped up for the duration of the integration period, reducing the voltage across the capacitor and allowing a greater amount of photocurrent to be integrated.
The Wyles approach suffers from several drawbacks. The integrating capacitors must be able to operate with both plates electrically accessible, so that the voltage ramp can be applied. This effectively excludes the use of r a MOSFET configured as an inversion capacitor, since the ramp voltage can bias the MOSFET below its threshold voltage. A capacitor made from two polysilicon layers above the substrate can be employed, but the thick oxide dielectric layer required by this type of capacitor lowers its capacitance per unit area. The preferred capacitor implementation for Wyles' circuit uses a gate electrode and a substrate diffusion as plates, with gate oxide as a dielectric, but fabricating such a capacitor requires special processing and significantly reduces yield.